The disclosure relates to the field of functional verification and prototyping of integrated circuits and in particular to the generation of circuit descriptions of field-programmable gate arrays (FPGAs).
The functional verification and prototyping of complex integrated circuits (also known as application specific integrated circuits (ASIC)) is usually done with emulation systems. These emulation systems are constituted of a hardware part, the emulator, which will behave like the circuit under verification, and a software compiler which is used to map a description of the circuit onto the physical resources available in the emulator.
Some emulators are made of numerous field-programmable gate arrays, FPGAs (typically from 9 to 800 FPGAs in the Synopsys ZeBu-Server family of emulators) interconnected through Printed Circuit Boards and/or cables. These FPGAs can be general purpose FPGAs such as Xilinx virtex7 FPGAs, or custom FPGAs specially designed by the emulator vendor. The main tasks of the compiler are the partitioning of the circuit into multiple sub-circuits, which will be mapped each on one FPGA, and the routing of the signals in the circuit which join different sub-circuits mapped on different FPGAs on the physical inter FPGA connections.
Recently, a new generation of multi-die FPGAs was introduced, based on a stacked silicon technology. The multiple identical dies which contain common FPGA logic resources are interconnected through a Silicon Interposer. The number of inter-die connections is high (around 13000), but it may not be sufficient to map highly connected sub-circuits on a multi-die based FPGA. The impact of this limited number of connections is increased in emulators made of several tens, potentially several hundreds, of FPGAs. If the compilation of a single FPGA fails due to the need of a very high inter-die connectivity, the mapping of the complex circuit on the emulator is stalled.
A potential solution to this problem would be to iterate on the partitioning of the circuit on the multiple FPGAs until the use of inter-die connections is sufficiently reduced on each FPGA to enable the FPGA compilation process. But this potential solution may lead to extremely long compilation time of the circuit on the emulator.
Another potential solution would be to lower the size of the sub-designs mapped on the FPGAs, thus to increase the number of FPGA used to map the complete design, so as to allow the FPGA compiler to optimize the mapping of the sub-circuit on the dies of the FPGA. But this solution leads to an increased cost of the hardware used to map a design.